

This course will help you understand the
fundamentals of environmental impact assessment of electronics, and the
basic instincts that you must develop to design more sustainable
devices.

As part of the GreenChips-EDU's training program, Grenoble INP and Aedvices are launching a new course that aims to introduce the fundamentals of verification in semiconductor design. In this course, you will learn:
- What verification is
- Why verification is needed
- When we have to do verification
- Who is doing verification
- How we do verification
- Globally you will get foundation of digital verification
Learning Objectives:
Students are able to explain why verification is needed and to understand the foundations of verification
Course Details:
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Course duration |
1h |
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Target Audience
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Students at masters level and professionals |
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Course training language
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English |
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Assessment type
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Self-assessment |

As part of the GreenChips-EDU program, this microelectronics course introduces the overall digital verification process and explains its role in validating digital integrated circuits before fabrication. By the end of this course, students will be able to understand and apply the overall digital verification process to verify and validate digital designs

As part of the GreenChips-EDU's training program, Grenoble INP and Aedvices are launching a new course that aims to understand the main aspects of verification in semiconductor design. In this course you will learn:
- What does mean System-on-Chip level verification
- What is a system
- What is the difference between System verification and block level verification
- In this in Introduction to SoC level Verification we will address these questions, giving some backgrounds and examples

As part of the GreenChips-EDU's training program, Grenoble INP and Aedvices are launching a new course that aims to understand the main aspects of verification in semiconductor design. In this course you will learn:
- The main categories of IPs you can find in a System On a Chip
- and for each a high level view of what needs to be verified at SoC level
